Our
project relied heavily on hardware and open source software
provided by Flex Radio.
The following are some links from Flex-Radio.com that were
most monumental to our project.
Main Flex Radio Website:
http://flex-radio.com
Flex Radio Download center
http://www.flex-radio.com/Download/
A Software Defined Radio for the Masses, Part 1; QEX, July/August
2002
http://flex-radio.com/articles_files/SDRFMP1.pdf
A Software Defined Radio for the Masses, Part 2; QEX, Sept/Oct
2002
http://flex-radio.com/articles_files/SDRFMP2.pdf
A Software Defined Radio for the Masses, Part 3; QEX, Nov/Dec
2002
http://flex-radio.com/articles_files/SDRFMP3.pdf
A Software Defined Radio for the Masses, Part 4; QEX, Mar/Apr
2003
http://flex-radio.com/articles_files/SDRFMP4.pdf
Some additional Resources used for Research:
Comblock.com
http://www.comblock.com
Xilinx.com
http://www.xilinx.com
Vanu Inc
http://www.vanu.com
SDR Forum
http://www.sdrforum.org
Tri-Band RF Testbed at Stevens Institute of Technology
http://attila.stevens-tech.edu/wireless/testbed
The
following are some links to VHDL experiments implemented
using FPGA boards
1.http://courses.ece.uiuc.edu/ece249/info/perform_vhdl.htm
Using the XFA100 FPGA board, it's an experiments to look
for numbers of flip-flops
and the total equivalent gate counts as well as the maximum
frequency
2.
http://ece.gmu.edu/courses/ECE449/Lab2/449exp2.html
Blinking LEDs
3.
http://ece.gmu.edu/courses/ECE449/Lab3/449exp3.html
Introduction of FSM
4.
http://ece.gmu.edu/courses/ECE449/Lab3/449exp4.html
A pump controller using FSM
5.
http://ece.gmu.edu/courses/ECE449/Lab3/449exp5.html
Program of a pulse generator
6.
http://ece.gmu.edu/courses/ECE449/Lab3/449exp6.html
VGA signal generator
7.
http://ece.gmu.edu/courses/ECE449/Lab3/449exp7.html
RC5 encryption
8.
http://www.cse.psu.edu/~cg478/03sp/hw/pj1/pj1.htm
http://www.cse.psu.edu/~cg478/03sp/hw/pj1/ee478Proj1.txt
Project of implementation of the 28 bit program counter
design.
9.
http://bear.ces.cwru.edu/eecs_317/project11.html
Parking controller
10.
http://bear.ces.cwru.edu/eecs_317/project12.html
Design of an alarm clock
11.
http://www.cse.psu.edu/~cg478/03sp/hw/pj2/pj2.htm
Implements and demonstrate the Phase Lock Loop (PLL)
circuit
12.
http://www.itee.uq.edu.au/~comp3100/
=>lab experiments => prac 8
BCD Adder in VHDL and FPGA (Using Xilinx FPGA board)
13.
http://www.itee.uq.edu.au/~comp3100/
=>lab experiments => prac 9
Race Timer
14.
http://www.itee.uq.edu.au/~comp3100/
=>lab experiments =>prac 10
Auto-ranging digital frequency meter in VHDL and FPGA
